The present invention generally relates to placing output signals of a circuit design on output pins of a device, and more particularly to placing output signals having different voltage levels.
Example complex programmable logic devices (CPLD) are found in the XC9500 family of CPLDs from Xilinx. The XC9500 CPLDs include input/output blocks (IOBs), function blocks (FBs), and a switch matrix for interconnecting the function blocks and I/O blocks. Such a switch matrix is described in U.S. Pat. No. 5,563,528, entitled, Multiplexer for Programmable Logic Device, to Diba et al. The inputs to the switch matrix are input pins from the IOBs and feedbacks from the FBs.
The semiconductor industry standard operating voltage has in the past been 5 volts, and all devices on a system board have operated at 5 volts. The IOBs were designed to interface with structures outside the chip using 5 volts as a power supply voltage. However, the industry is presently migrating to lower voltages for faster operation at lower power. Rather than all chips in a system operating at a single voltage, different chips operating at different power supply voltages may be present in a single system. It may be desirable for a CPLD in a mixed-voltage system to interface with chips operating at different voltage levels.
Some devices in the XC9500 family of CPLDs have multiple output banks, also referenced as xe2x80x9cphysical output banksxe2x80x9d (POBs). An output bank includes a set of output pins that are driven by the same output power supply (VCCIO). All the pins of a function block belong to the same physical output bank and are all driven by the same VCCIO. Each physical output bank is programmable to a selected VCCIO. By setting the VCCIO of certain physical output banks to the same voltage level, the banks can be viewed as merged into one xe2x80x9clogical output bankxe2x80x9d (LOB).
As with any programmable logic device, a CPLD has a limited number of pin resources. Thus, for most any design, a placement solution that makes efficient use of pin resources while satisfying the output banking requirements is desirable. A method and apparatus that addresses aforementioned problems, as well as other related problems, are therefore desirable.
In various embodiments, a method and apparatus are provided for placing output signals having different voltage levels on output pins of a programmable logic device (PLD). The PLD includes a plurality of function blocks (FBs), and each FB includes one or more output pins. The output signals are organized into logical output banks (LOBs), the output signals in each LOB having a common voltage level. Each of the FBs is associated with an LOB. For each FB, one or more unplaced signals are selected for placement in the FB as a function of a number of unplaced output signals in the LOB with which the FB is associated (xe2x80x9ccurrent LOBxe2x80x9d), a number of output pins in FBs associated with LOBs other than the current LOB, and a number of output pins in all FBs that are associated with the current LOB and that have no assigned output signals.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims, which follow.